1. Field of the Invention
This invention relates to the field of integrated circuit testing. More particularly, the present invention describes a method for using wafer navigation while testing integrated circuits in order to reduce the overall testing times of integrated circuits.
2. Background
It is common practice in the manufacturing of integrated circuits (IC's) to test the functionality of circuits on the silicon wafer prior to the wafer being divided into smaller, individual dice for packaging. Dice that are identified during a test as having a fatal defect are tagged, either by physically placing a drop of ink on the defective dice or by setting a flag in a test data base, so that the defective dice are rejected prior to the packaging process.
Improvements in integrated circuit technology have resulted in the gradual increase in the overall size of individual wafers and the dramatic decrease in the die area required to perform a given function. Thus, greater numbers of more complex circuits are now present on each wafer. For example, the number of bits stored in a leading edge Dynamic Random Access Memory (DRAM) has increased about a thousand times over the past fifteen years.
As integrated circuit technology has evolved, manufacturing and inspection techniques have been developed for improving the yield of good dice and for identifying the physical origins of failures. The desire to develop these technical improvements has been largely driven by a reduction in physical dimensions and increase in integrated circuit complexity that rendered earlier inspection techniques ineffective. Two advances that are particularly relevant to the present invention will now be described.
The first advance relates to the identification of physical defects. For a number of years this inspection was performed by operators using microscopes. The information gained from these inspections is then used to make process adjustments and to rework individual wafers in attempts to repair observed defects.
As the feature size on integrated circuit dice has shrunk, individual defects that were large enough to affect circuit functionality has become more difficult to observe with a microscope. In addition, the number of features to be observed has increased exponentially with time, thus overburdening the inspection personnel. Thus, automated inspection techniques were introduced as a replacement.
Inspection stations utilizing automated inspection techniques generally depend upon optical techniques which allow inspection of large areas of the wafer simultaneously in order to provide high throughputs which decreases the cost of inspection per layer per wafer.
These inspection stations are computer controlled and are capable of generating reports on defect density by defect size by process layer inspected for each wafer inspected. This information, together with the location of the defects, is stored in a large data base which is used with statistical techniques to provide feedback to manufacturing personnel. This feedback might indicate when to perform maintenance operations or when a manufacturing tool is out of statistical control and consequently in need of intervention by a technician.
A second advance in technology that has been developed is navigation for failure analysis. For Large-Scale Integrated (LSI) circuitry, finding the location of an identified defect is not difficult. For example, an LSI memory of 1 Kbit capacity typically has 32 rows and 32 columns, the intersection of each row and column containing a memory cell. If a memory cell located on the ninth row and seventeenth column fails, it is a relatively simple task to find the failing cell by counting the rows and columns.
In comparison, an Ultra Large-Scale Integrated (ULSI) memory of 16 Mbit capacity typically has 4096 rows and 4096 columns, with each intersection of a row and a column containing a memory cell. If a failure were to occur on the cell located at the intersection of row 1247 and column 2783, for example, locating the cell by manually counting rows and columns would be extremely tedious and prone to error.
To overcome this problem, software that finds an identified location on a die from known fiducial marks by using the information from the layout data base was developed. This software is commonly referred to as navigation software by analogy with a map. Commonly, a wafer is mounted on a movable stage that allows precision adjustment of the displacement so that a defect that has been identified can be placed at the center of the field of view of an optical microscope or scanning electron microscope so that a failing location can be closely inspected or so that detailed electrical testing of the failing location, often referred to as microprobing, can be carried out.
Despite improvements in testing techniques, the time needed to test each die has increased significantly, and the equipment required to perform the test has increased in sophistication, resulting in a significant increase in testing costs. In order to reduce testing costs, techniques such as parallel testing and design for test have been developed. In spite of these cost reduction efforts, the overall cost of testing continues to increase.
Although these advances in testing methodology have somewhat reduced the time and effort required to test circuits disposed on a silicon wafer, significant time is still spent in determining whether any identified defect on the wafer is fatal to any given die. It would therefore be beneficial to provide a method for testing integrated circuits which significantly reduces the testing time over the prior art, thus providing greater throughput.